Changeset 460
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Added further readme files

Committed by:  ncorbic
Date:  Oct 15 2005 * 00:19 (over 3 years ago)

Affected files:

libsangoma/trunk/README (unified diff)

r435r460
11 * Needs wanpipe 2.3.4 or higher to compile.
22 It can be downloaded here. Its still in beta.
33 ftp.sangoma.com/linux/custom/tdm_api/wanpipe-beta1-2.3.4.tgz
4
5
6
7 ===============================================================
8
9
10 The TDM API is only supported from wanpipe release:
11
12 wanpipe-beta1-2.3.4.tgz
13
14
15 Installation
16 ============
17
18 1. Untar wanpipe-beta1-2.3.4.tgz or greater
19
20 2. Run ./Setup install
21
22 3. Choose all default parameters
23
24
25 4. Compilation Mode: Choose DEFAULT
26
27 Note that Wanpipe TDM_API uses just the AFT drivers
28 and doesn't need ZAPTEL support.
29 Thus, the TDM (Zaptel) driver is optional.
30
31 5. Proceed with default parameters.
32
33
34 6. Use Configuration file below to configure your
35 TDM_API driver.
36
37
38 Configuration
39 =============
40
41 Please refer to the APPENDIX Config File
42
43
44 LibSangoma
45 ==========
46
47 The libsangoma is a standalone library that
48 a developer would use to communicate the the
49 TDM API sockets.
50
51 LibSangoma Installation
52 -----------------------
53 ./configure
54 make
55 make install
56
57
58 LibSangoma Functions
59 --------------------
60
61 /*-----------SOCKET HANDLING FUNCTIONS-------------*/
62
63 /* Socket Create/Bind functions
64 * create_socket: Creates a socket on specific span and first available chan
65 * create_socket_by_name: Creates a socket on a specific chan name
66 * create_socket_intr: Creates a socket on specific chan based on span/chan numbers
67 */
68 int sangoma_create_socket(int span);
69 int sangoma_create_socket_by_name(char *device, char *card);
70 int sangoma_create_socket_intr(int span, int intr);
71
72 /* Socket Rx/Tx functions
73 * sendmsg: tx header + data from separate buffers
74 * recvmsg: rx header + data to separate buffers
75 * wrte: tx header + data from single buffer
76 * read: rx header + data to single buffer
77 */
78 int sangoma_sendmsg_socket(int sock, void *hdrbuf, int hdrlen,
79 void *databuf, int datalen, int flag);
80 int sangoma_readmsg_socket(int sock, void *hdrbuf, int hdrlen,
81 void *databuf, int datalen, int flag);
82 int sangoma_write_socket(int sock, void *data, int len);
83 int sangoma_read_socket(int sock, void *data, int len);
84
85 /* Decodec Span/Chan from interface name */
86 int sangoma_interface_toi(char *interface, int *span, int *chan);
87
88
89 /*----------------TDM API COMMANDS PER CHAN---------------*/
90
91 /* Get Full TDM API configuration per chan */
92 int sangoma_get_full_cfg(int sock, wanpipe_tdm_api_t *tdm_api);
93
94 /* Get/Set TDM Codec per chan */
95 int sangoma_tdm_set_codec(int sock, wanpipe_tdm_api_t *tdm_api, int codec);
96 int sangoma_tdm_get_codec(int sock, wanpipe_tdm_api_t *tdm_api);
97
98 /* Get/Set HW Tx/Rx Period in milliseconds */
99 int sangoma_tdm_set_hw_period(int sock, wanpipe_tdm_api_t *tdm_api, int period);
100 int sangoma_tdm_get_hw_period(int sock, wanpipe_tdm_api_t *tdm_api);
101
102 /* Get user MTU/MRU values in bytes */
103 int sangoma_tdm_get_usr_mtu_mru(int sock, wanpipe_tdm_api_t *tdm_api);
104
105 /* Not supported yet */
106 int sangoma_tdm_set_power_level(int sock, wanpipe_tdm_api_t *tdm_api, int power);
107 int sangoma_tdm_get_power_level(int sock, wanpipe_tdm_api_t *tdm_api);
108
109
110
111 TMDV API Sample Code
112 ====================
113
114 Refer to the example/ directory
115
116 make
117
118
119
120 APPENDIX
121 ========
122
123 A104 - TDMV API Config File
124 A101/2 - TDMV API Config File
125
126
127 Save the config file below into: /etc/wanpipe/wanpipe1.conf
128
129
130 ********************CUT HERE************************************
131
132 #================================================
133 # WANPIPE1 Configuration File
134 #================================================
135
136
137 [devices]
138 wanpipe1 = WAN_AFT, Comment #WAN_AFT_TE1 - Indicates A104 card
139 #WAN_AFT - Indicates A101/2 card
140
141 [interfaces]
142
143 #-------- DRIVER INTERFACE DEFINITIONS --------------------------------
144
145 w1g1 = wanpipe1, , TDM_API, Comment
146 w1g2 = wanpipe1, , TDM_API, Comment
147 w1g3 = wanpipe1, , TDM_API, Comment
148 w1g4 = wanpipe1, , TDM_API, Comment
149 w1g5 = wanpipe1, , TDM_API, Comment
150 w1g6 = wanpipe1, , TDM_API, Comment
151 w1g7 = wanpipe1, , TDM_API, Comment
152 w1g8 = wanpipe1, , TDM_API, Comment
153 w1g9 = wanpipe1, , TDM_API, Comment
154 w1g10 = wanpipe1, , TDM_API, Comment
155 w1g11 = wanpipe1, , TDM_API, Comment
156 w1g12 = wanpipe1, , TDM_API, Comment
157 w1g13 = wanpipe1, , TDM_API, Comment
158 w1g14 = wanpipe1, , TDM_API, Comment
159 w1g15 = wanpipe1, , TDM_API, Comment
160 w1g16 = wanpipe1, , TDM_API, Comment
161 w1g17 = wanpipe1, , TDM_API, Comment
162 w1g18 = wanpipe1, , TDM_API, Comment
163 w1g19 = wanpipe1, , TDM_API, Comment
164 w1g20 = wanpipe1, , TDM_API, Comment
165 w1g21 = wanpipe1, , TDM_API, Comment
166 w1g22 = wanpipe1, , TDM_API, Comment
167 w1g23 = wanpipe1, , TDM_API, Comment
168 w1g24 = wanpipe1, , API, Comment
169
170 [wanpipe1]
171
172 #-------- DEVICE / DRIVER BINDING ----------------------------------
173
174 CARD_TYPE = AFT #AFT: Same for all aft cards must
175 #This value must be hardcoed to AFT for all
176 #aft cards.
177
178 S514CPU = B #Used by A101/2 driver to determine T1/E1 port
179 #A - port 1
180 #B - port 2
181 #For A104 driver: Always set this value to A!
182
183 AUTO_PCISLOT = YES #Auto detect PCI/BUS info for this card type
184 #NO - disable this option
185 #YES- enable this option
186 # if enabled bottom two options
187 # PCISLOT and PCIBUS will not be used.
188 # Therefore one can set the to arbitrary value
189 # or remove them all together.
190
191 PCISLOT = 2 #PCI SLOT Number:
192 #Valid values = any number
193
194 PCIBUS = 2 #PCI BUS Number:
195 #Valid values = any number
196
197 #--------------FRONT END SETUP -----------------------------------
198
199
200 FE_MEDIA = T1 #Front End Type:
201 #T1 - set front end for T1 mode
202 #E1 - set front end for E1 mode
203
204 FE_LCODE = B8ZS #Front End Line Coding
205 #If T1: B8ZS or AMI
206 # E1: HDB3 or AMI
207
208 FE_FRAME = ESF #Front End Framing
209 #If T1: ESF or D4
210 # E1: CRC4 or NCRC4
211
212 FE_LINE = 4 #Front End Line number.
213 #Used by A104 driver to determine T1/E1 port
214 #Valid values are: 1-4
215 #
216 #The A101/2 driver doesn't use this option
217 #so one should hardcode it to 1 or
218 #remove it all together.
219
220
221 TE_CLOCK = NORMAL #T1/E1 Clock Source
222 #NORMAL - slave clock, clock is received from telco
223 # This is always the DEFAULT
224 #MASTER - master clcok, use hw oscillator clock
225 # Only used in back to back mode or
226 # when specified by telco.
227
228
229 TE_REF_CLOCK = 0 #T1/E1 Reference Clock Source
230 #This option allows one to use the incoming clock
231 #from a different port as a clock source to this
232 #port. FOR THIS OPTION TO WORK: TE_CLOCK=MASTER
233 #Valid options: 0 - disable
234 # 1-4 - use clock from particular port
235
236
237 ACTIVE_CH = ALL #Specify T1/E1 Active channels (timeslots)
238 #Since AFT cards support channelization this
239 #option MUST BE HARDCODED TO: ALL!
240
241
242 TE_HIGHIMPEDANCE = NO #Set the Front Ent chip in High Impedance mode
243 #used for datascoping:
244 #NO - Disable high impedance mode (DEFAULT)
245 #YES - Enable hight impedance mode
246 # (only if you know what you are doing)
247
248 LBO = 0DB #Front End Line Buildout
249 # 0db (Default)
250 # 7.5dB
251 # 15dB
252 # 22.5dB
253 # 0-110ft
254 # 110-220ft
255 # 220-330ft
256 # 330-440ft
257 # 440-550ft
258 # 550-660ft
259
260
261 FE_TXTRISTATE = NO #Front End Tri-State Mode
262 #Disable front end chip TX mode
263 #Used for datascoping or connecting multiple ports
264 #together where one port is operating normally and others
265 #are tristated, thus only receiving.
266 #NO - Disable tristae mode
267 #YES- Enable tristate mode
268
269
270 #------------ MISC DRIVER OPTIONS --------------------------
271
272
273 MTU = 1500 #Global MTU Value
274 #Note: This value is overwritten by the
275 # interface MTU value below if it exists.
276 #Values: any number [ suggested 128 - 4086 ]
277
278 IGNORE_FRONT_END = NO #Ignore Fronte End State
279 #NO - Do not ignore front end state,
280 # therefore if state changes, change the
281 # state of the above protocol.
282 #YES- Igonore front end state
283 # Thus if front end goes down, the protocol
284 # will not know.
285
286
287
288 #------------ VOICE INTERFACE CONFIG --------------------------
289 #Each interface corresponds to a specific T1/E1 timeslot
290 #For T1: Interface 24 must be configured for PRI
291 #For E1: Interface 16 must be configured for PRI
292
293 [w1g1]
294 PROTOCOL = HDLC #Protocol: HDLC : Hardcoded Value
295
296 HDLC_STREAMING = NO #HDLC Engine Control
297 #(NOT USED if interface is in TDM_API mode)
298 #NO: Disable HDLC Engine: Transparet (VOICE) mode
299 #YES: Enable HDLC Engine: PRI mode
300
301 ACTIVE_CH = 1 #Hardware Timeslot Number
302 #For T1: 1-24
303 #For E1: 1-31
304
305 IDLE_FLAG = 0x7E #Idle Flag to be transmitted
306 #in Tx underrun condition.
307
308 MTU = 80 #Maximum Tx Size
309 #API will/must transmit in MTU chunks
310 #1ms = 8
311 #10ms = 80 (Default)
312
313 MRU = 80 #Maximum Rx Size
314 #API will receive data in MRU chunks
315 #1ms = 8
316 #10ms = 80 (Default)
317
318
319 [w1g2]
320 PROTOCOL = HDLC
321 HDLC_STREAMING = NO
322 ACTIVE_CH = 2
323 IDLE_FLAG = 0x7E
324 MTU = 80
325 MRU = 80
326
327
328 [w1g3]
329 PROTOCOL = HDLC
330 HDLC_STREAMING = NO
331 ACTIVE_CH = 3
332 IDLE_FLAG = 0x7E
333 MTU = 80
334 MRU = 80
335
336
337
338 [w1g4]
339 PROTOCOL = HDLC
340 HDLC_STREAMING = NO
341 ACTIVE_CH = 4
342 IDLE_FLAG = 0x7E
343 MTU = 80
344 MRU = 80
345
346
347
348 [w1g5]
349 PROTOCOL = HDLC
350 HDLC_STREAMING = NO
351 ACTIVE_CH = 5
352 IDLE_FLAG = 0x7E
353 MTU = 80
354 MRU = 80
355
356
357
358 [w1g6]
359 PROTOCOL = HDLC
360 HDLC_STREAMING = NO
361 ACTIVE_CH = 6
362 IDLE_FLAG = 0x7E
363 MTU = 80
364 MRU = 80
365
366
367 [w1g7]
368 PROTOCOL = HDLC
369 HDLC_STREAMING = NO
370 ACTIVE_CH = 7
371 IDLE_FLAG = 0x7E
372 MTU = 80
373 MRU = 80
374
375
376 [w1g8]
377 PROTOCOL = HDLC
378 HDLC_STREAMING = NO
379 ACTIVE_CH = 8
380 IDLE_FLAG = 0x7E
381 MTU = 80
382 MRU = 80
383
384
385 [w1g9]
386 PROTOCOL = HDLC
387 HDLC_STREAMING = NO
388 ACTIVE_CH = 9
389 IDLE_FLAG = 0x7E
390 MTU = 80
391 MRU = 80
392
393
394 [w1g10]
395 PROTOCOL = HDLC
396 HDLC_STREAMING = NO
397 ACTIVE_CH = 10
398 IDLE_FLAG = 0x7E
399 MTU = 80
400 MRU = 80
401
402
403 [w1g11]
404 PROTOCOL = HDLC
405 HDLC_STREAMING = NO
406 ACTIVE_CH = 11
407 IDLE_FLAG = 0x7E
408 MTU = 80
409 MRU = 80
410
411
412 [w1g12]
413 PROTOCOL = HDLC
414 HDLC_STREAMING = NO
415 ACTIVE_CH = 12
416 IDLE_FLAG = 0x7E
417 MTU = 80
418 MRU = 80
419
420
421 [w1g13]
422 PROTOCOL = HDLC
423 HDLC_STREAMING = NO
424 ACTIVE_CH = 13
425 IDLE_FLAG = 0x7E
426 MTU = 80
427 MRU = 80
428
429
430 [w1g14]
431 PROTOCOL = HDLC
432 HDLC_STREAMING = NO
433 ACTIVE_CH = 14
434 IDLE_FLAG = 0x7E
435 MTU = 80
436 MRU = 80
437
438
439 [w1g15]
440 PROTOCOL = HDLC
441 HDLC_STREAMING = NO
442 ACTIVE_CH = 15
443 IDLE_FLAG = 0x7E
444 MTU = 80
445 MRU = 80
446
447
448 [w1g16]
449 PROTOCOL = HDLC
450 HDLC_STREAMING = NO
451 ACTIVE_CH = 16
452 IDLE_FLAG = 0x7E
453 MTU = 80
454 MRU = 80
455
456
457 [w1g17]
458 PROTOCOL = HDLC
459 HDLC_STREAMING = NO
460 ACTIVE_CH = 17
461 IDLE_FLAG = 0x7E
462 MTU = 80
463 MRU = 80
464
465
466 [w1g18]
467 PROTOCOL = HDLC
468 HDLC_STREAMING = NO
469 ACTIVE_CH = 18
470 IDLE_FLAG = 0x7E
471 MTU = 80
472 MRU = 80
473
474
475 [w1g19]
476 PROTOCOL = HDLC
477 HDLC_STREAMING = NO
478 ACTIVE_CH = 19
479 IDLE_FLAG = 0x7E
480 MTU = 80
481 MRU = 80
482
483
484 [w1g20]
485 PROTOCOL = HDLC
486 HDLC_STREAMING = NO
487 ACTIVE_CH = 20
488 IDLE_FLAG = 0x7E
489 MTU = 80
490 MRU = 80
491
492
493 [w1g21]
494 PROTOCOL = HDLC
495 HDLC_STREAMING = NO
496 ACTIVE_CH = 21
497 IDLE_FLAG = 0x7E
498 MTU = 80
499 MRU = 80
500
501
502 [w1g22]
503 PROTOCOL = HDLC
504 HDLC_STREAMING = NO
505 ACTIVE_CH = 22
506 IDLE_FLAG = 0x7E
507 MTU = 80
508 MRU = 80
509
510
511 [w1g23]
512 PROTOCOL = HDLC
513 HDLC_STREAMING = NO
514 ACTIVE_CH = 23
515 IDLE_FLAG = 0x7E
516 MTU = 80
517 MRU = 80
518
519
520 #--------------- PRI/DCHAN CONFIGURATION ---------------
521
522 [w1g24]
523
524 PROTOCOL = HDLC #Protocol: HDLC : Hardcoded Value
525
526 HDLC_STREAMING = YES #HDLC Engine Control
527 #NO: Disable HDLC Engine: Transparet (VOICE) mode
528 #YES: Enable HDLC Engine: PRI mode (Default)
529
530 ACTIVE_CH = 24 #Hardware PRI Timeslot Number
531 #For T1: 24
532 #For E1: 16
533
534 IDLE_FLAG = 0x7E #Idle Flag to be transmitted
535 #in Tx underrun condition.
536 #Used in VOICE mode only.
537
538 MTU = 1500 #Maximum Tx Size
539 #Corresponds to maximum TX HDLC packet size
540
541 MRU = 1500 #Maximum Rx Size
542 #Corresponds to maximum RX HDLC packet size
543
544
545
546 ********************CUT HERE************************************
547